| PhD, Computer Science University of Edinburgh, UK | TBD | 2019 - present |
| Masters Degree, Computer Science University of Edinburgh, UK | Dist. | 2018 - 2019 |
| Bacherlor of Science (Hons), Electronic and Telecom. Engineering University of Moratuwa, Sri lanka | 3.97/4.2 | 2011 - 2016 |
| Research Engineer | Systems for machine learning | CodeGen | Jan 2018 - present |
| Electronic Engineer | Hardware (ASIC/FPGA) for network analytics | Paraqum | Apr 2016 - Dec 2017 |
| Google Summer of Code Student | Middleware for distributed machine learning | WSO2 | Feb 2016 - Sep 2016 |
| Engineering Intern | Program synthesis, automation & verification | Synopsys | Oct 2014 - Apr 2015 |
| Programming | C/C++, Java, Python, bash, tcl |
| Hardware | HDL, Verilog, System Verilog, VHDL |
| Tools | Linux, RISC, RISC-V and Open Source Developments |
| Program Committee - TACO 2023 |
| Computer Architecture and Design (CARD) | Parallel Architectures |