[Under Submission] - Fast Recoverable Disaggregated Memory Transactions
[ASPLOS'20] - Lazy Release Persistency Mahesh Dananjaya, Vasilis Gavrielatos, Arpit Joshi, Vijay Nagarajan The 24th ACM conference on Architectural Support for Programming Languages and Operating Systems, Laussane, Switzerland, 2020. [Acceptance Rate=18%] [pdf][ppt][video][third-party blog][industry adaptation]
[THESIS'23] - TANDEM: Taming Failures in Next-Generation Datacenters with Emerging Memory Mahesh Dananjaya The University of Edinburgh, United Kingdom
[THESIS'19] - Release Persistency Mahesh Dananjaya The University of Edinburgh, United Kingdom [MSc Dissertation Award] [submitted-pdf]
Other (First or Equally-Contributed Author)
[ASAP'18] - Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutional Neural Networks Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual The 29th IEEE International Conference on Application-specific Systems, Architectures and Processors, Milan, Italy, 2018. [pdf]
[LANMAN'17] - SDN based Operator Assisted Offloading Platform for Multi-Controller 5G Networks Madhusanka Liyanage, Mahesh Dananjaya, Jude Okwuibe, Mika Ylianttila The 23rd IEEE International Symposium on Local and Metropolitan Area Networks, Osaka, Japan, 2017. [pdf]
[NFV-SDN'16] - High Performance Flow Matching Architecture for OpenFlow Data Plane Viduranga Wijekoon, Mahesh Dananjaya, Pramodya Kariyawasam, Sasika Iddamalgoda, Ajith Pasqual The 2nd IEEE International Conference on Network Function Virtualization and Software Defined Networks, Palo Alto, California, USA, 2016 [pdf]
[THESIS'16] - OpenFlow Aware Network Processor with a custom RISC ISA Mahesh Dananjaya, Viduranga Wijekoon, Pramodya Kariyawasam, Sasika Iddamalgoda, Ajith Pasqual University of Moratuwa, Sri Lanka, 2016 [pdf]